SinePulse Digital Design Engineer
SinePulse is an emerging company in the field of IT, Radio Frequency and Embedded System engineering. SinePulse has business and development center in different countries keeping head office in Munich, Germany. SinePulse is going to launch off-shore development center in Dhaka, Bangladesh to boost up research activities in the field of smart technologies for the future.
The selected candidate must have present working knowledge related to developing Static Timing Analysis (STA) constraints, Clock Tree Synthesis, timing analysis, timing ECO’s and full chip timing closure. Current and/or past experience with RTL design, synthesis, equivalency checking is also preferred. Experience with floor-planning and CTS is a plus.
- Analyze RTL designs and prepare block/chip level timing constraints.
- Synthesize RTL designs and perform equivalency checking/debug.
- Analyze pre-layout timing and recommend implementation improvements to the RTL designers.
- Analyze post-layout timing, develop timing ECOs and work closely with layout engineers to achieve full chip timing closure.
- Develop floor-planning and CTS guidelines for layout.
Additionally the candidate must fulfill following characteristics:
- Experience developing block and chip level SDC constraints for functional and test modes.
- Experience performing detailed timing analysis and creating timing ECO’s to drive timing closure.
- Experience with synthesis and equivalency checking.
- Synopsis: IC Compiler, Design Compiter, PrimeTime, Apache Redhawk, Prime Time, Power Constraints, Clock Tree Synthesis
- Cadence: Conformal Flow (LEC)
- Mentor: Calibre
- Atrenta: Spyglass
Place of work:
Based on Experience
As soon as possible
No. of Positions: