SinePulse Electrical Package Designer
You will be responsible for the development of our new chip/package co-design flow for leadframe packages, which bridges the gap between mechanical CAD (package design environment in AutoCAD) and electrical CAD (chip design environment in Cadence Virtuoso or Cadence Encounter), including connectivity entry, physical layout design of the leadframe and the bonding diagram, DRC, LVS, and the link to electrical and thermal simulation of the complete system of chip and package.
- 1+ years experience in AutoCAD
- Experience with Candence tool
- Knowledge on semiconductor chip packaging technology is desired.
- Experience with 3D modeling and simulation (e.g. FEM tools like Ansys Q3D, HFSS) is desirable.